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winbond smbus gpio controller w83l603g W83L604G revision: 1.0 date: august 2006
w83l603g/W83L604G publication release date: august 2006 - i - revision 1.0 w83l603g/W83L604G datasheet revision history pages dates version web version main contents 1 n.a. aug./06 1.0 1.0 init ial version for customer
w83l603g/W83L604G - ii - table of contents- 1. general des cription ......................................................................................................... 1 2. features ....................................................................................................................... .......... 1 2.1 general features ............................................................................................................... ......1 2.2 key specifications ............................................................................................................. .......1 3. pin config uration .............................................................................................................. .2 4. pin descri ption................................................................................................................ ..... 3 4.1 w83l603g ....................................................................................................................... ........3 4.2 W83L604G ....................................................................................................................... ........4 5. architecture d escription .............................................................................................. 5 6. function desc riptions.................................................................................................... 10 6.1 access interface ............................................................................................................... ......10 6.1.1 write a data into w83l6 03g/W83L604G re gister ........................................................10 6.1.2 read a data from w83l603g /W83L604G r egister .......................................................10 6.2 gpi/o application mode: .......................................................................................................1 1 6.2.1 gpo out put .................................................................................................................. 11 6.2.2 int out put..................................................................................................................... 11 6.2.3 gpi interrupt stat us....................................................................................................... 11 7. dc and ac specif ication.................................................................................................. 12 7.1 absolute maximum ratings ...................................................................................................12 7.2 power supply current consumption .....................................................................................12 7.3 dc characteristics ............................................................................................................. ....12 7.4 ac characteristics............................................................................................................. .....14 8. package dimensio n outline........................................................................................... 15 9. ordering info rmatio n..................................................................................................... 17 10. how to read the top marking...................................................................................... 17 11. typical applicatio n circui t........................................................................................... 18
w83l603g/W83L604G publication release date: august 2006 - 1 - revision 1.0 1. general description the w83l603g & W83L604G are general purpose input/output ics with smbus tm . w83l603g provides 8 gpi/o pins, W83L604G provides 14 gpi/o pins. w83l603g & W83L604G both provide smbus tm address setting pins to set the address during power- on reset or from external reset. w83l603g / W83L604G smbus tm address is: w83l603g & W83L604G also provide an interrupt to inform system that a transition occurs on general purpose input pins. by w83l603g & W83L604G, flashing led output and beep function are also supported. the part number with an affix of ?g? is the lead-free package product. 2. features 2.1 general features ? smbustm compliance with 3.3v voltage levels ? flexible gpio pin support, w83l603g prov ides 8 pins, W83L604G provides 14 pins. ? interrupt notification support for system event occurs ? support general purpose output setting for level or pulse mode ? support interrupt output setting for level or pulse mode ? support internal power-on reset or external rst# pin reset. ? support flashing led output ? support pc beep output ? chip power down mode support ? 14-sop lead-free package for w83l603g (rohs compliable) ? 20-ssop lead-free package for W83L604G (rohs compliable) 2.2 key specifications ? supply voltage is 3.3v ? operating supply current is 150 ua typ. ? operating temperature is from 0 c to 70 c 0 0 1 1 a2 a1 a0 r/w
w83l603g/W83L604G - 2 - 3. pin configuration
w83l603g/W83L604G publication release date: august 2006 - 3 - revision 1.0 4. pin description in ts ttl level schmitt-trigger input pin i/od 12ts ttl level bi-directional pin open drain output with 12 ma sink capability and schmitt- trigger level input i/o 12t ttl level bi-directional pin bi-directional output with 12 ma source-sink capability i/o(d) 16t ttl level bi-directional pin bi-directional (or open drain) output with 16 ma (source-) sink capability i/o(d) 12t ttl level bi-directional pin bi-directional (or open drain) output with 12 ma (source-) sink capability od 12 open drain output pin with 12 ma sink capability 4.1 w83l603g pin symbol i/o function 1 scl in ts smbus clock. 2 sda i/od 12ts smbus bi-directional data. 3 gp10/led0 i/o(d) 16t general purpose i/o. ; led output 4 gp11/led1 i/o(d) 16t general purpose i/o. ; led output 5 gp12/led2 i/o(d) 16t general purpose i/o. ; led output 6 gp13/led3 i/o(d) 16t general purpose i/o. ; led output 7 vss pwr power pin. 8 gp14/beep i/o(d) 16t general purpose i/o. ; beep output 9 gp15 / a2 i/o 12t general purpose i/o.; strapping pin for smbus address bit 2, this pin is internal weak pull down during hardware reset. 10 gp16 / a1 i/o 12t general purpose i/o.; strapping pin for smbus address bit 1, this pin is internal weak pull down during hardware reset. 11 gp17 / a0 i/o 12t general purpose i/o.; strapping pin for smbus address bit 0, this pin is internal weak pull down during hardware reset. 12 int# od 12 auto-generated interrupt signal when detecting a transition on gp inputs. 13 rst# in ts system reset signal input. low level must be greater than 0.1us. 14 3vdd pwr power pin.
w83l603g/W83L604G - 4 - 4.2 W83L604G pin symbol i/o function 1 scl in ts smbus clock. 2 sda i/od 12ts smbus bi-directional data. 3 gp10/led0 i/o(d) 16t general purpose i/o. ; led output 4 gp11/led1 i/o(d) 16t general purpose i/o. ; led output 5 gp12/led2 i/o(d) 16t general purpose i/o. ; led output 6 gp13/led3 i/o(d) 16t general purpose i/o. ; led output 7 vss pwr power pin. 8 gp20 i/o(d) 12t general purpose i/o. 9 gp21 i/o(d) 12t general purpose i/o. 10 gp22 i/o(d) 12t general purpose i/o. 11 gp23 i/o(d) 12t general purpose i/o. 12 gp24 i/o(d) 12t general purpose i/o. 13 gp25 i/o(d) 12t general purpose i/o. 14 gp14/beep i/o(d) 16t general purpose i/o. ; beep output 15 gp15 / a2 i/o 12t general purpose i/o.; strapping pin for smbus address bit 2, this pin is internal weak pull down during hardware reset. 16 gp16 / a1 i/o 12t general purpose i/o.; strapping pin for smbus address bit 1, this pin is internal weak pull down during hardware reset. 17 gp17 / a0 i/o 12t general purpose i/o.; strapping pin for smbus address bit 0, this pin is internal weak pull down during hardware reset. 18 int# od 12 auto-generated interrupt signal when detecting a transition on gp inputs. 19 rst# in ts system reset signal input. low level must be greater than 0.1us. 20 3vdd pwr power pin.
w83l603g/W83L604G publication release date: august 2006 - 5 - revision 1.0 5. architecture description register 00h ? gp1 input port register bit 7 6 5 4 3 2 1 0 r/w ro ro ro ro ro ro ro ro *this register reflects the respective gpi1x pin level. register 01h ? gp1 output port register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register 02h ? gp1 polarity inversion register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 *refer to section 6.2.1 for respec tive gpo1x pin type implementation. register 03h ? gp1 input/output configuration register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 1 1 1 1 1 1 1 1 *this register configures the res pective gpio1x pin as input mode (?1?; by default) or output mode (?0?). register 04h ? gp1 output style register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 *this register configures the respec tive gpo1x pins as level (?0?; by default) or pulse (?1?) output style. *set output port register (cr01) to ?0? bef ore switch the output style to pulse mode. register 05h ? gp1 output mode register bit 7 6 5 4 3 2 1 0 r/w rfu rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0
w83l603g/W83L604G - 6 - bit4-bit0: configures the respecti ve gpo1x output pads function as op en-drain (?0?; by default) or push- pull (?1?) mode. bit6-5: gp14 / beep multi-functi on configurati on register =11, beep frequency = 4khz; tone = 250 hz. =10, beep frequency = 2khz; tone = 10 hz. =01, beep frequency = 1khz / 500 hz; tone= 1 hz. =00, beep function is disabled on gp14. bit7: reserved fo r future use. register 06h ? gp1 interrupt control register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 * this register configures the res pective gpi1x pin interrupt control as disable (?0?; by default) or enable (?1?). *clear interrupt status register (cr07) before set to enable. register 07h ? gp1 interrupt status register bit 7 6 5 4 3 2 1 0 r/w r/clr r/clr r/clr r/clr r/clr r/clr r/clr r/clr *the registers are read clear. *refer to section 6.2.3 for implementation. register 08h ? gp11-gp13 / led multi-function configuration register bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 bit7-6: gp13 / led multi-func tion configuration register =11, gp13 functions led output of 2hz clock, 50% duty cycle. =10, gp13 functions led output of 1hz clock, 50% duty cycle. =01, gp13 functions led output of 1/2 hz clock, 50% duty cycle. =00, led function is disabled on gp13. (default) bit5-4: gp12 / led multi-func tion configuration register =11, gp12 functions led output of 2hz clock, 50% duty cycle. =10, gp12 functions led output of 1hz clock, 50% duty cycle. =01, gp12 functions led output of 1/2 hz clock, 50% duty cycle. =00, led function is disabled on gp12. (default) bit3-2: gp11 / led multi-func tion configuration register =11, gp11 functions led output of 2hz clock, 50% duty cycle. =10, gp11 functions led output of 1hz clock, 50% duty cycle. =01, gp11 functions led output of 1/2 hz clock, 50% duty cycle. =00, led function is disabled on gp11. (default) bit1-0: gp10 / led multi-func tion configuration register =11, gp10 functions led output of 2hz clock, 50% duty cycle. =10, gp10 functions led output of 1hz clock, 50% duty cycle. =01, gp10 functions led output of 1/2 hz clock, 50% duty cycle. =00, led function is disabled on gp10. (default)
w83l603g/W83L604G publication release date: august 2006 - 7 - revision 1.0 register 09h ? gp1 input latch data register bit 7 6 5 4 3 2 1 0 r/w ro ro ro ro ro ro ro ro default 0 0 0 0 0 0 0 0 *this register reflects the latch value of gp1x pins during hardware reset. register 10h ? gp2 input port register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w na ro ro ro ro ro ro *this register reflects the respective gpi2x pin level. register 11h ? gp2 output port register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 0 0 0 0 0 0 register 12h ? gp2 polarity inversion register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 0 0 0 0 0 0 *refer to section 6.2.1 for respec tive gpo2x pin type implementation. register 13h ? gp2 input/output configuration register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 1 1 1 1 1 1 *this register configures the res pective gpio2x pin as input mode (?1?; by default) or output mode (?0?). register 14h ? gp2 output style register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 0 0 0 0 0 0 *this register configures the respec tive gpo2x pins as level (?0?; by default) or pulse (?1?) output style. *set output port register (cr11) to ?0? bef ore switch the output style to pulse mode.
w83l603g/W83L604G - 8 - register 15h ? gp2 output mode register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 0 0 0 0 0 0 *this register configures the respec tive gpo2x output pads function as open-drain (?0?; by default) or push-pull (?1?) mode. register 16h ? gp2 interrupt control register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w rw rw rw rw rw rw default na 0 0 0 0 0 0 * this register configures the res pective gpi2x pin interrupt control as disable (?0?; by default) or enable (?1?). *clear interrupt status register (cr17) before set to enable. register 17h ? gp2 interrupt status register (for W83L604G only) bit 7 6 5 4 3 2 1 0 r/w na r/clr r/clr r/cl r r/clr r/clr r/clr *the registers are read clear. *refer to section 6.2.3 for implementation. register 20h ? chip id (high byte; 95h for W83L604G, 96h for w83l603g) bit 7 6 5 4 3 2 1 0 r/w ro ro ro ro ro ro ro ro default 1 0 0 1 0 1 0/1 1/0 register 21h ? chip id (low byte; 92h) bit 7 6 5 4 3 2 1 0 r/w ro ro ro ro ro ro ro ro default 1 0 0 1 0 0 0 1
w83l603g/W83L604G publication release date: august 2006 - 9 - revision 1.0 register 22h ? global configuration register bit 7 6 5 4 3 2 1 0 r/w wo rfu rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 bit7: write ?1? to issue a software reset. bit6: reserved fo r future use. bit5: low power enable bit. the internal clock generator will shutdown while the bit is set. in the low- power mode, the functions of smbus, led, beep, and all signals configured as the pulse mode will not work. bit4: wake-up enable. if the bit is set, low-power enable bit (bit-5) can be cleared whenever interrupt event is triggered on gpi pin. to enable the interr upt control register (cr06,cr16) is necessary. bit3: interrupt polarity bit. refer to section 7.2.2 for int pin type implementation. bit2: this bit configures the int signal output as level (?0?; by default) or pulse (?1?) style. bit1: gp2 registers mask enable. set ?1? will mask the rst# signal for all gp2 registers. (10h ~ 17h) bit0: gp1 registers mask enable. set ?1? will mask the rst# signal for all gp1 registers. (00h ~ 08h) *bit1 and bit0 will not be reset by rst#.
w83l603g/W83L604G - 10 - 6. function descriptions 6.1 access interface w83l603g/W83L604G provides a two-wired serial interface which is compliant with smbus tm write byte and read byte protocol. 6.1.1 write a data into w83l603g/W83L604G register 6.1.2 read a data from w83l603g/W83L604G register
w83l603g/W83L604G publication release date: august 2006 - 11 - revision 1.0 6.2 gpi/o application mode: 6.2.1 gpo output take reference table for gpo style and polarity function. gpo output style polarity output port register output value at pin wave 0 0 0 1 1 0 1 level 1 1 0 0 write 1 active pulse 1 write 1 active *the gpo pulse mode output waveform width is 0.5us. 6.2.2 int output take reference table for int output mode and polarity function. int output mode polarity output wave 0 0 level 1 1 0 low pulse pulse 1 high pulse *in level mode, if int is activated, it will be de- activated when interrupt stat us registers are read. *in pulse mode, interrupt will be activated again un less all enabled interrupt status registers are read. *the int pulse mode output waveform width is 0.25us. 6.2.3 gpi interrupt status once a transition occurs at gpi input pins, interrupt status registers (cr07, cr17) will be set. at the mean time, if interrupt function is enable (cr06, cr16), the int pin will generate an interrupt waveform. reading these interrupt status registers will self clear and reset interrupt. if an interrupt occurs but never read the interrupt status regi sters, the interrupt will not be generated again.
w83l603g/W83L604G - 12 - 7. dc and ac specification 7.1 absolute maximum ratings parameter rating unit power supply voltage 3.3 10% v input voltage 3.3 10% v operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 7.2 power supply current consumption (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) parameter typical unit normal mode 150 ua power down mode 10 ua note : the typical value is measured by w hole gpio pins output without load. 7.3 dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) in ts - ttl level schmitt-trigger input pin parameter sym. min. typ. max. unit conditions input low voltage v il 0.8 v v dd = 3.3 v input high voltage v ih 2.0 v v dd = 3.3 v input high leakage i lih +10 a v in = v dd input low leakage i lil -10 a v in = 0 v i/od 12ts - ttl level bi-direction pin with 12ma sink capability and schmitt-trigger input input low voltage v il 0.8 v v dd = 3.3 v input high voltage v ih 2.0 v v dd = 3.3 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 a v in = v dd input low leakage i lil -10 a v in = 0 v
w83l603g/W83L604G publication release date: august 2006 - 13 - revision 1.0 dc characteristics , continued. i/o 12t - ttl level bi-direction pin with 12ma source-sink capability input low voltage v il 0.8 v v dd = 3.3 v input high voltage v ih 2.0 v v dd = 3.3 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = 12 ma input high leakage i lih +15 a v in = 3.3 v input low leakage i lil -15 a v in = 0 v i/o(d) 16t - ttl level bi-direction pin with 16ma source-sink capability input low voltage v il 0.8 v v dd = 3.3 v input high voltage v ih 2.0 v v dd = 3.3 v output low voltage v ol 0.4 v i ol = 16 ma output high voltage v oh 2.4 v i oh = 16 ma input high leakage i lih +10 a v in = 3.3 v input low leakage i lil -10 a v in = 0 v i/o(d) 12t - ttl level bi-direction pin with 12ma source-sink capability input low voltage v il 0.8 v v dd = 3.3 v input high voltage v ih 2.0 v v dd = 3.3 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = 12 ma input high leakage i lih +10 a v in = 3.3 v input low leakage i lil -10 a v in = 0 v od 12 - open-drain output pin with 12ma sink capability output low voltage v ol 0.4 v iol = 12 ma
w83l603g/W83L604G - 14 - 7.4 ac characteristics serial bus timing diagram valid data scl sda in sda out t hd;sta t scl t su;dat t su;sto t hd;dat serial bus timing diagram t r t f serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sta 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
w83l603g/W83L604G publication release date: august 2006 - 15 - revision 1.0 8. package dimension outline winbond provides two packages for customers thank contain 14-sop and 20-ssop. 14l sop-150mil for w83l603g seating plane l o c 0.25 gauge plane control demensions are in milmeters . 4.00 0.25 0.51 0.25 e c b a1 3.80 0.19 0.33 0.10 0.157 0.010 0.020 0.010 0.150 0.008 0.013 0.004 max. dimension in mm 1.75 a symbol min. 1.35 dimension in inch 0.069 min. 0.053 max. 1.27 0.10 6.20 l y h 08 0.40 5.80 e 1.27 bsc 0.050 0.004 0.244 0 0.016 0.228 8 0.050 bsc e d 8.55 8.75 0.337 0.344 e h e 1 14 8 7 a1 a e b d y
w83l603g/W83L604G - 16 - 20l ssop-209mil for W83L604G 0 0.002 0.197 0.291 7.80 0 7.40 8 8.20 5.30 b e d c 6.90 5.00 a1 a2 a 5.60 7.50 7.20 2.00 1.85 8 0.323 0.307 0.073 0.079 0.220 0.272 0.295 0.283 0.209 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.05 e l l1 y 0.009 0.015 0.004 0.010 0.021 0.030 0.050 0.004 0.22 0.38 0.09 0.25 0.65 0.0256 0.55 0.75 1.25 0.10 h e 0.95 0.037 1.75 1.65 0.065 0.069 1 20 d e e y b a1 a2 a seating plane dteail a l l1 detail a seating plane e h 10 11 b
w83l603g/W83L604G publication release date: august 2006 - 17 - revision 1.0 9. ordering information part number package type production flow w83l603g 14-sop (leadfree) commercial, 0 c to +70 c W83L604G 20-ssop (leadfree) commercial, 0 c to +70 c 10. how to read the top marking left line: winbond logo 1 st line: w83l603g ? the part number for leadfree product 2 nd line: chip lot no 3 rd line: tracking code 524 g b 524 : packages assembled in year 05?, week 24 g : assembly house id; o means ose, g means gr, etc. b : the ic version left line: winbond logo 1 st line: W83L604G ? the part number for leadfree product 2 nd line: chip lot no 3 rd line: tracking code 524 g b 524 : packages assembled in year 05?, week 24 g : assembly house id; o means ose, g means gr, etc. b : the ic version w83l603g 212345678 524gb W83L604G 212345678 524gb
w83l603g/W83L604G - 18 - 11. typical application circuit gp16 sclk gp10 d2 led rst# 3vcc or sclk c3 0.1u 3vcc 3vcc 3vcc r8 10k gp12 d4 led r3 4.7k *connect to system interrupt input. sdat rst# r6 4.7k c2 10u gp24 u1 w83l603s 1 2 3 4 5 6 7 26 27 28 29 30 31 32 sclk sdat led0/gp10 led1/gp11 led2/gp12 led3/gp13 vss beep/gp14 a2/gp15 a1/gp16 a0/gp17 int# rst# 3vdd 3vcc sy stem_int# rst# gp14 *connect to system reset control output. gp21 3vcc gp17 c1 1u gp11 gp12 gp17 gp10 gp20 led group int# w83l603s/w83l604r 0.1 b 11 monday , july 11, 2005 title size document number rev date: sheet of gp10 *mount the pull up resistor to set the address bit to 1. 3vcc gp15 c6 10u r4 0 r5 0 int# 3vcc sclk r13 330 1 2 d1 led sy stem_rst# pc beep 3vcc r11 330 1 2 c4 10p sy stem_sdat gp22 gp16 smbus interface gp25 r2 4.7k a0 sdat r14 330 1 2 r9 10k gp13 gp11 gp14 r7 10k r1 10k 3vcc r10 150 r12 330 1 2 c5 10p a1 gp15 u2 w83l604r 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 31 32 sclk sdat led0/gp10 led1/gp11 led2/gp12 led3/gp13 vss gp20 gp21 gp22 gp23 gp24 gp25 beep/gp14 a2/gp15 a1/gp16 a0/gp17 int# rst# 3vdd int# gp13 *the w83l603s/w83l604r gp14 pin default setting is gp input , the buzzer application circuit is option to selected buzzer type and gp14 type. gp23 sdat inbond winbond electronics corp. a2 3vcc rst# *rst# source low level has to greater than 0.1us width. gp17 gp15 sy stem_sclk gp16 *example for set the gp14 to gpo push-pull type. buzzer_vcc c7 0.1u smbus address selection 3vcc gp11 d3 led buzzer1 ac-1205g gp12 gp13 q1 npn 3vcc gp14 <br> w83l603g/<a href='http://www.datasheet.hk/search.php?part=w83l604g&stype=part'>W83L604G</a> publication release date: august 2006 - 19 - revision 1.0 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. <br></td> </tr> </table> <table border="0" width="980" id="table32" style="font-size:1px" height="10"> <tr> <td></td> </tr> </table> <table border="0" width="980" id="table31" style="font-size:1px" height="40"> <tr> <td background="images/bg03.gif"> <p align="right"><br> <font color="#FF0000"><a href="#top">▲Up To Search▲</a> </font></td> </tr> </table> <table border="0" width="980" id="table27"> <tr> <td> </td> </tr> <tr> <td> <b><font size="5">Price & Availability of W83L604G </font></b> <a target="_blank" href="https://www.findchips.com/search/W83L604G"><img border="0" src="images/fc_logo.jpg" width="265" height="25"></a></td> </tr> <tr> <td><script src="http://www.findchips.com/api/inventory/search/W83L604G?limit=5&partner=18"></script> <script>document.getElementById("poweredBy").style.visibility="hidden";</script></td> </tr> </table> </div> <div align="center"> <table border="0" width="980" id="table13" style="font-size:12px"> <tr> <td> <table border="0" width="980" id="table26" style="font-size:1px"> <tr> <td background="images/bg03.gif"></td> </tr> </table> </td> </tr> <tr> <td> <p align="right">All Rights Reserved © <span lang="zh-cn"> IC-ON-LINE 2003 - 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